For a long time, the chip manufacturers had an inclination to simplify the hardware and rely on the software adapting and optimizing. But for decades this bid failed. Now we have the unrelenting AI capable of finetuning kernels relatively quickly. Maybe simpler hw will work this time? Note: not sure if TPU/NPU is not only simple but also too limited.
yipinwong•Aug 21, 2026
This is a type of article that is HN worthy and came to HN for initially because I don't even understand a third of content there. Giving me inspiration to dive deeper.
SEriously, I don't understand it (yet) lol.
nazgulsenpai•Aug 21, 2026
That's the best feeling -- idly clicking through looking for that one rabbit hole to fall down then stumbling upon a gem like this. I noticed this the first time on copetti.org articles about game console architectures: know nothing, look every jargon or acronym up as you read along, end up with 42 tabs and a basic high-level understanding of the topic by the end.
brcmthrowaway•Aug 21, 2026
Ctrl+F PCIe BAR.. nothing.
porridgeraisin•Aug 21, 2026
This is talking about HBM/GDDR
KK7NIL•Aug 21, 2026
a.k.a. VRAM
brcmthrowaway•Aug 21, 2026
Something needs to be transferred from sysmem right?
wmf•Aug 21, 2026
That's probably PCIe DMA initiated by the GPU so I don't think BAR is used.
porridgeraisin•Aug 21, 2026
Pcie dma uses BAR registers setup by cpu. It will contain information about the physical memory address for one. On newer systems, there is NVLINK C2C which is more tightly integrated and less general.
Regardless, my point was the the article is about vram.
However, there is one situation when vram access itself uses the bar, to be fair.
When you do P2P dma, code (kernel, either the inbuilt version or the one in the nvidia driver) running on the cpu sets up the DMA engines's GART to contain the BAR1s of the other.
snigacookie•Aug 21, 2026
Can someone help me understand why I spent 5 minutes reading something that I still don't understand?
Link for the ELI5 version?
wmf•Aug 21, 2026
There isn't really an ELI5 version of computer architecture but you could start with the book Inside the Machine by Jon Stokes. Then you can get into SIMT.
> Little of the detail of this path is documented by NVIDIA, at least not to the level that we’d like, so we’ll determine it by running timing experiments on the hardware itself
7 Comments
SEriously, I don't understand it (yet) lol.
Regardless, my point was the the article is about vram.
However, there is one situation when vram access itself uses the bar, to be fair. When you do P2P dma, code (kernel, either the inbuilt version or the one in the nvidia driver) running on the cpu sets up the DMA engines's GART to contain the BAR1s of the other.
Link for the ELI5 version?
"what every programmer should know about memory" https://github.com/Ty-Chen/Reading-List/blob/master/What%20e...
Here’s a clean version: https://people.freebsd.org/~lstewart/articles/cpumemory.pdf
Or you could just use the AMD isa.